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PLL FREQUENCY SHNTHESIZER FOR PAGER
S5T8808A
INTRODUCTION
S5T8808A is a superior low-power-programmable PLL frequency synthesizer which can be used in a high performance Wide Area Pager system. S5T8808A consists of 2 kinds of divider block including a 17bit Shift register, 16-bit Latch, 14/16-bits Counter, Prescaler, and a phase detector block including a Phase detector, Lock detector and a Charge pump.
16-TSSOP-0044
FEATURES
* Maximum operating frequency: 120MHz @ 500mVP-P, VDD1 = 0.95V, VDD2 = 3.0V 165MHz @ 500mVP-P, VDD1 = 1.0V, VDD2 = 3.0V
( Magnification = 1 : 4 )
* *
On-chip reference oscillator supports external crystal which oscillates up to 18MHz Superior supply current: FFIN = 90MHz, IDD1 = 0.6mA (Typ.) @ VDD1 = 1.0V, VDD2 = 3.0V FFIN = 150MHz, IDD1 = 0.9mA (Typ.) @ VDD1 = 1.0V, VDD2 = 3.0V Operating voltage: VDD1 = 0.95 ~ 2.0V and VDD2 = 2.0 ~ 3.3V Reference frequency counter divider range: 1 / 28 ~ 1 / 65532 (Multiple 4) But, the Divider range with FRC_High state: 1 / 7 ~ 1 / 16383 RX frequency counter divider range: 1 / 28 ~ 1 / 65535 Package type: 16-TSSOP (0.65mm)
* * * *
ORDERING INFORMATION
Device +S5T8808A01-R0B0
+: New Product
Package 16-TSSOP-0044
Operating Temperature -25C to +75C
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S5T8808A
PLL FREQUENCY SHNTHESIZER FOR PAGE
BLOCK DIAGRAM
OSCI 1 OSCO 2 VDD1 VDD2
Amp
14-Bit Divider ( R - counter ) FnFr Lock Detector
15 10
Fr LDT
FRC
14
VDD2
3
16-Bit Latch
NC
16 Schmitt Trigger
16 Phase Detector
EN DATA CLK
13 12 11 4 16 Charge Pump 5 PDA PDP Shift Register * 17- Bit
VSS
6 16-Bit Latch
16 7 8 VDD1
FnFr
9
NC
Fin VDD1
Amp
16-Bit Divider ( N - counter )
14
Fn
2
PLL FREQUENCY SHNTHESIZER FOR PAGER
S5T8808A
PIN CONFIGURATION
OSCI OSCO VDD2 PDA PDP VSS Fin VDD1
1 2 3 4 5 6 7 8
S5T8808A KS8808AD
16 15 14 13 12 11 10 9
NC Fr Fn EN DATA CLK LDT NC
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S5T8808A
PLL FREQUENCY SHNTHESIZER FOR PAGE
PIN DESCRIPTION
Pin No 1 2 3 4 Symbol OSCI OSCO VDD2 PDA I/O I O - O Description These input / output pins generate the reference frequency. In case of OSCI Pin, external reference frequency can be used through the AC coupling. The highest potential supply terminal that can be supplied up to 2.0 ~ 3.3V, except for VDD1. The Output of RX Phase detector terminal for active loop filter There are 3-kinds of output signal states according to Rx Loop Error; - If Fr > Fn (Fr is leading), the output is negative pulse state, - If Fr < Fn (Fr is lagging), the output is positive pulse state, - If Fr = Fn (the same phase), the output is high impedance state. The Output of RX Phase detector terminal for passive loop filter There are 3-kinds of output signal states according to Rx Loop Error; - If Fr > Fn (Fr is lagging), the output is negative pulse state, - If Fr < Fn (Fr is leading), the output is positive pulse state, - If Fr = Fn (the same phase), the output is high impedance state. Ground terminal Input terminal for 16 bit Divider from VCO. Mostly, VCO output should be input through the AC coupling and the minimum input level is 500mVP-P (in case of 90MHz) Voltage supply terminal for Oscillator and Fin block. This pin can be supplied up to 0.95 ~ 2.0V from VSS. No Connection Lock detector is also on output of the Phase Detector. The LOW state of this output shows unlock status, which is the error width between the Ref. signal and the VCO output signal. These pins are controlled by the -controller and it also has Schmitt Trigger architecture. Internally biased pull-down. The features of these pins are as follows: Clock input for 17-bit Shift Register, Serial data input (it include FnFr-on / off and FRC), and Latch enable input (User selectable EN1 or EN2). Output terminal for divider value of N-counter. To control the output On/Off, the FnFr bit of the Reference register can be programmed. When FnFr bit is set to High, this output shows low level. Output terminal of divider value of N-counter. To control the output On/Off, the FnFr bit of the Reference register can be programmed. When FnFr bit is set to High, this output shows low level. No Connection. Internally biased pull-up.
5
PDP
O
6 7
VSS Fin
- I
8 9 10
VDD1 NC LDT
- - O
11 12 13
CLK DATA EN
I I I
14
Fn
O
15
Fr
O
16
NC
-
4
PLL FREQUENCY SHNTHESIZER FOR PAGER
S5T8808A
ABSOLUTE MAXIMUM RATINGS
Characteristic Supply Voltage Input Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VDD ~ VDD2 VI PD TOPR TSTG Value -0.3 ~ +4.0 VSS - 0.3 ~ VDD + 0.3 350 -25 ~ +75 -40 ~ +125 Unit V V mW C C
ELECTRICAL CHARACTERISTICS
(Ta = 25C, VDD1 = 1.0V, VDD2 = 3.0V, unless otherwise specified) Characteristic Operating voltage Symbol VDD1 VDD2 Operating current IDD1 IDD2 Test Conditions - - FOSCI = 12.8MHz FFIN = 90MHz @ 0.3VP-P FFIN = 150MHz VDD1 = 1.0V VDD2 = 1.0V VDD1 = 0V, VDD2 = 3.0V - - VIH = VDD1 VIL = 0V FFIN = 0.5VP-P VDD1 = 0.95V VDD1 = 1.0V FOSCI Output current (PDA, PDP) Output current (Fr, Fn, LDT) Setup-time (DATA-CLK, CLK-EN) Hold time IOH1 IOL1 IOH2 IOL2 ts tH VOSCI = 0.5VP-P VOH = 0.4V VOL = VDD1 - 0.4V VOH = 0.4V VOL = VDD1 - 0.4V - - Min. 0.95 2.0 - - - - VDD3-0.3 - - - - 7 1.0 1.0 0.1 0.1 2 2 Typ. 1.0 3.0 0.6 0.9 - - - - - - - - - - - - - - Max. 2.0 3.3 - - A V A mA Unit V
Standby current Input Voltage (DATA, CLK, EN, BS) Input current (Fin, Xin) Input frequency
ISB VIL VIH VIH VIL FFIN
10 0.3 - 20 20 120 165 18 - - - - - -
MHz
mA
mA S S
5
S5T8808A
PLL FREQUENCY SHNTHESIZER FOR PAGE
FUNCTIONAL DESCTRIPTION
Table 1. N-Counter Register Program Scheme (17 bits) Bit Name Description Function RxD Rx. Program Data (ND 15 ~ ND 0) 16 Bit Programmable Rx. N-Counter Data Bit 16 (ND 15) ~ Bit 1 (ND 0) PMC Program Mode Control 0: Rx. N-Counter 1: Ref. R-Counter Bit 0 (LSB)
PMC = 0 16-bit N_Counter
Rx.16Bit N_Counter Data ( ND15 ~ ND0 ) PMC
DATA
MSB LSB
1 CLK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
positive edge triggered
EN1 or EN2
Figure 1. Rx. Register Programming Timing * * Programmable N-counter consists of 2-bits Swallow Counter, 4/5 Dual modulars Prescaler and 14-bits Main Counter The Divide Ratio is; N = (P + 1) x S + P (M - S) = PM + S; -- P = Dual Modulars Prescaler (4) -- S = 2-bits Swallow Counter value (0 ~ 3) -- M = 14-bits (7 ~ 16383) -- N = Programmable N-Counter value (N > S; 28 ~ 65535)
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PLL FREQUENCY SHNTHESIZER FOR PAGER
S5T8808A
*
Ex 1) In case of 14-bits program, Fc = 325.300MHz, Multiplier = 4, Fin = 75.975MHz [Fin Freq. / Ref. Frequ.] = 75.975MHz / 6.25kHz = 12156
2
13
2 0 1 0 1 1 1 1 0 1 1 1 1 1
0
2 0
1
2 0
0
0 MSB
0 LSB
PMC bit
Main CNT 14 - bits
Swallow CNT 2-bits
* *
According to the above equation, 12156/4(P) = 3039 & left = 0 that means, Swallow CNT value is "0", Main CNT value is "3039". The PMC bit is Program Control Bit, if [0], the N-Counter will be Enabled. Table 2. R-Counter Register Program Scheme (17 bits) Bit Name Description Function Bit 16 (RD 13) ~ Bit 3 (RD 0) RefD Ref. Program Data (RD 13 ~ RD 0) 14 Bit Programmable Ref. R-Counter FRC Bit 2 FnFr Control Mode 0: No FRC (OSCI/4R) 1: FRC (OSCI/R) Table 3. Control Mode FRC 0 0 1 1 FnFr 0 1 0 1 Fn (Pin 14) Fn out (Fin / N counter) LOW Fn out (Fin / N-counter) LOW Fr (Pin 15) Fr out (OSCI / 4 x R) LOW Fr out (OSCI / R) LOW 0: Fn, Fr function 1: Fn, Fr Low Bit 1 Bit 0 (LSB) PMC Program mode control 0: Rx. N-Counter 1: Ref. R-Counter
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S5T8808A
PLL FREQUENCY SHNTHESIZER FOR PAGE
Ref .14Bit R_Counter Data ( RD13 ~ RD0 )
FRC FnFr PMC
DATA
MSB LSB
1 CLK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
positive edge triggered
EN1 or EN2 * It is possible to use Optional selection of EN1, EN2 ( when used EN )
Figure 2. Ref. Register Programming Timing
NOTE: It is possible to use Optional selection of EN1, EN2 (when used EN)
* *
The Input Reference Frequency (X-tal Oscillator) will divided by 1/4 Prescaler, and then divided by Preprogrammed R-counter value once more. Programmable R-Counter consists of Fixed 1/4 Prescaler, 14-bits Programmable Counter When FRC = 0, Fixed 1/4 Prescaler is used and 14-bits counter & can divide Multiple 4 RD = 4, R = 28 (=4 x 7) ~ 65532 -- (Min. Divide value:7) When FRC = 1, Fixed 1/4 Prescaler isn't used, but using 14-bits counter & Can divide all value RD = R = 7 ~ 16384 [All value] --- (Min. Divide value:7)
*
Ex 1) FRC = 0, In case of 14-bits Program, Fosc = 12.8MHz and fixed 1/4 prescaler is used [(Osc. Freq. / Prescaler) / Ref. Freq.] = [(12.8MHz / 4) / 6.25kHz] = 512
2
13
2 0 0 0 1 0 0 0 0 0 0 0 0 0
0
0 MSB
0
0
1 LSB
FRC FnFr PMC bit R - counter 14 - bits
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PLL FREQUENCY SHNTHESIZER FOR PAGER
S5T8808A
*
Ex 2) FRC = 1, In case of 14-bits Program, Fosc = 12.8MHz and fixed 1/4 prescaler is not used [Osc. Freq. / Ref. Freq.] = [12.8MHz / 6.25kHz] = 2048
2
13
2 0 1 0 0 0 0 0 0 0 0 0 0 0
0
0 MSB
1
0
1 LSB
R - counter 14 - bits
FRC FnFr PMC bit
* The PMC bit is program Control Bit, if [1], the R-Counter will be Enabled
Serial DATA Input Timing & Phase Detector / Lock Detector Output Waveforms
DATA tH 50% CLK
tsu EN 1
50%
~ ~
Figure 3. Serial Data Input Timing
~ ~
tsu
~ ~
~ ~
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S5T8808A
PLL FREQUENCY SHNTHESIZER FOR PAGE
The architecture of R-Count Divider
D0 ------------- D13
OSCI 12.8MHz 12.8MHz X-Tal
1/4 Prescaler
3.2MHz
14 bits Counter
Fr 6.25KHz
FRC
OSCO
Figure 4. R-CNT architecture VCO output Frequency fVCO = N x fVCO / RD fVCO = VCO output frequency fOSC = X-tal Oscillator Frequency RD = Programmable Reference R-counter value N = Programmable N-counter value
Phase Detector / Lock Detector
OSCI
1 2
1/ 4 CNT
14 Bit R - Divider
15
FR
OSCO
FRC Fr LD
10
Lock Detector
Phase Detector Fn
5 4
PDP PDA
16 Bit Programmabel N_Counter Fin
7
4/5 Counter
2 bits Swallow Counter
14 Bit N - Divider
14
FN
Figure 5. Phase Detector / Lock Detector Block Diagram
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PLL FREQUENCY SHNTHESIZER FOR PAGER
S5T8808A
Fr
Fn
PDP
PDA
LD GND
VDD1
Figure 6. Phase Detector / Lock Detector Output Waveforms
NOTES: 1. Phase detector always compares the Phase difference of N-counter with R-counter, and set to High or Low state as much as the phase difference. 2. The LD output set to Low level same as Phase detector error width.
11
S5T8808A
PLL FREQUENCY SHNTHESIZER FOR PAGE
APPLICATION CIRCUIT
From Antenna
1st MIXer
X
To IF IC
KS8808A S5T8808A
1 OSCI 2 OSCO 3V 3 VDD2 4 PDA NC Fr Fn EN DATA CLK LDT NC 16 15 14 13 12 11 10 9 Monitoring MICOM Monitoring Monitoring
Multiplier
VCO
5 PDP 6 Vss 7 Fin 8 VDD1
1V
12

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